1. Field of Invention
The present invention relates to a shift register. More particularly, the present invention relates to a flat panel display, a display driving apparatus thereof and a shift register thereof.
2. Description of Related Art
As the flat panel display (for example, liquid crystal display (LCD)) has such characteristics as being light, thin, small, low radiation and power saving, these features help save the space usage of office or home, and reduce the feeling of eye tiredness after a long time viewing. Therefore, the flat panel display has characteristic to fully substitute the conventional cathode ray tube (CRT).
FIG. 1A is a circuit diagram of a conventional shift register, which is implemented upon a glass substrate using low temperature poly silicon (LTPS) technology. Referring to FIG. 1A, the shift register can be adapted for the driving circuit of the flat panel display, for example, the gate driver for vertical scan of the liquid crystal display. FIG. 1A includes 5 stages of same shift registers, SR1, SR2, SR3, SR4, and SR5, respectively. Each shift register includes an input terminal In, clock signal input terminals CKA and CKB and an output terminal Out. FIG. 1A includes four clock signal wires respectively inputting a first clock signal CK1, a second clock signal CK2, a third clock signal CK3 and a fourth clock signal CK4. In addition, FIG. 1A also includes a start pulse wire SP.
FIG. 1B is a detailed circuit diagram of the conventional shift register SR1 in FIG. 1A, which is implemented upon a glass substrate using the low temperature poly silicon (LTPS) technology. The circuit comprises thin film transistors (TFT) 101, 102, 103 and a capacitor 104. The first source/drain of the TFT 101 is the input terminal In of the SR1. The second source/drain of the TFT 101 is coupled to the gate of the TFT 102. The gate of the TFT 101 is the clock signal input terminal CKA, and the gate of the TFT 101 is coupled to the gate of the TFT 103. The first source/drain of the TFT 102 is the clock signal input terminal CKB. The second source/drain of the TFT 102 is the output terminal Out of the SR1. The first source/drain of the TFT 103 is coupled to the second source/drain of the TFT 102. The second source/drain of the TFT 103 is the low level voltage input terminal VSS.
FIG. 1C is a clock diagram of the circuit in FIG. 1A. Referring to FIG. 1A, FIG. 1B, and FIG. 1C simultaneously, we presume that the low level of the voltage amplitude of the clock signal equals to VSS, and the high level of the voltage amplitude of the clock signal equals to VDD, and VDD>VSS. First, a start pulse on the start pulse wire SP is provided to the input terminal In, and at this time, the clock signal CK1 is at high level voltage (VDD). Accordingly, the TFT 101 and the TFT 103 are conducted so that the high level voltage is stored in the capacitor 104. When the clock signal CK1 turns to low level from high level, the clock signal CK3 also turns to high level from low level at the same time. As the capacitor 104 stores the high level voltage, the gate of the TFT 102 receives the high level voltage so that the high level voltage VDD on the clock signal CK3 is conducted to the output terminal Out. Accordingly, the next shift register SR2 starts to receive the high level voltage output from the output terminal Out.
Although the conventional technology has provided an architecture of shift registers, however, the architecture has one disadvantage. Referring to FIG. 1B, it can be learned from FIG. 1B that the clock signal CKB must be input from the source/drain of the TFT 102. Accordingly, the clock signal generator should have very strong driving power; however, the increase of the driving power would cause the increase of the layout area.